Professor Changhwan Shin from School of Electrical Engineering: "Chiplet Value Chain, A New Collaboration Model for Semiconductors"
관리자 2024.11.15 Views 21
Professor Changhwan Shin, a leading scholar in semiconductors and former outside director at SK Hynix, proposed a value chain centered on chiplet technology as a new collaboration model for the global semiconductor industry during the forum.
At the forum, held under the theme "Post-U.S. Presidential Election - Intensifying Hegemonic Competition" at Lotte Hotel in Sogong-dong, Jung-gu, Seoul, Professor Shin presented a scenario centered on chiplet technology as a new cooperation model for the semiconductor industry, which is at a crossroads of change due to the U.S.-China conflict.
Chiplet technology involves separating each necessary function from a large chip into several smaller chips, then integrating them into a single package. This approach allows for improved yield and cost savings, and enables the rapid development of high-performance semiconductors tailored to various uses, making it a key factor in the advanced packaging competition of back-end processes.
Professor Shin explained, "We could produce 28nm from China's SMIC, 3nm from Intel and TSMC, and 5nm from Samsung, then combine these three chips to create a computer with the desired performance. This is referred to as either chiplet or advanced packaging."
He added, "If a new chiplet value chain is formed and President-elect Donald Trump decides that it would be better to collaborate with China to create an AI computing system that fulfills desired capabilities rather than impose tariffs, then even under 'America First' or 'America Only' policies, opportunities for cooperation may arise."
He emphasized, "Chiplet technology can be an intermediate solution—not fully self-sufficient nor fully dependent. It allows each country to focus on its strengths while maintaining an overall cooperative structure."
He also added, "This allows semiconductor products to play a crucial role, much like salt, across various industries such as 5G, AI, autonomous vehicles, data centers, augmented reality (AR), and virtual reality (VR)."
Regarding the competition in semiconductor technology, Professor Shin noted that the industry is moving beyond miniaturization to an era of 3D chips that are stacked vertically.
In the case of DRAM, he pointed out that the ongoing miniaturization of planar DRAM is approaching its physical limits, leading to active development of new 3D DRAM structures to overcome these technological challenges.
Professor Shin projected, "By around 2030, DRAM will become 3D DRAM, and NAND flash, which can currently stack over 300 layers, will reach 400 layers the year after next, and conservatively speaking, about 500 layers by 2029."
He explained, "In line with the AI era, we will be able to stack various semiconductor chips vertically to deliver chips to customers within a set timeframe, matching the desired performance, power, area, and cost."